(b) Why are the two IPO steps different ?ДЄns: IPO optimizes timing by buffer insertion and cell resizing. (a) Why is this called 'In-Place Optimization' ? Q7: IPO (sometimes also referred to as 'In-Place Optimization') tries to optimize the design timing by buffering long wires, resizing cells, restructuring logic etc.Д®xplain how these IPO steps affect the quality of the design in terms of area, congestion, timing slack.

You could refer the paper 'Low-Cost Single-Layer Clock Trees With Exact Zero Elmore Delay Skew', Andrew B. The merging segment becomes a set of points with equal Elmore delay instead of just equal path length.

Q6: Extend the ZST-DME algorithm to embed a binary tree such that the Elmore delay from the root to each leaf of the tree is identical.ДЄns: You needed to mention that a new procedure is needed for calculating the Elmore delay assuming that certain merging points are chosen, instead of just the total downstream wire-length. Delay is independent of width because the 'w' term cancels out. wider segments near the root and narrower segments near the leaves. Can we reduce the Elmore delay by changing the width of a wire segment? Explain your answer.ДЄns: You needed to mention that by scaling different segments by different amounts, you can reduce the delay (e.g. Q5: Given a unit wire resistance 'r' and a unit wire capacitance 'c', a wire segment of length 'l' and width 'w' has resistance 'l/w' and capacitance 'cwl'. Or 'shared' resistances, 'recursive' calculations, etc) Mentioning something that shows that it can be done in linear time ('lumped' T = Sum over all nodes i in path (s,t) of Ri*Ci where Ci is the total capacitance in the sub tree rooted at node i, or alternatively, the sum over the capacitances at the nodes times the shared resistance between the path of interest and the path to the node. Q4: Give the linear time computation scheme for Elmore delay in an RC interconnect tree. Making sure we don't have false violations (false path, etc.) Logic re-structuring/Transformation (w/Resynthesis) - R earrange logic to meet timing constraints on critical paths of design Replication is done by connecting an identical cell to the same inputs as the original cell.Cloning clones the cell to divide the fanout load to improve the timing. Cloning - Cell cloning is a method of optimization that decreases the load of a very heavily loaded cell by replicating the cell. Transistor (cell) sizing - Cell sizing is the process of assigning a drive strength for a specific cell in the library to a cell instance in the design.If there is a low drive strength cell in the timing critical path then this cell is replaced by higher drive strength cell to reduce the timing violation. Pin swapping - Pin swapping optimization examines the slacks on the inputs of the gates on worst timing paths and optimizes the timing by swapping nets attached to the input pins, so the net with the least amount of slack is put on the fastest path through the gate without changing the function of the logic. Unmapping - Unmapping converts the technology-specific logic gates in the netlist to primitive logic gates on the timing critical paths. Mapping - Mapping converts primitive logic cells found in a netlist to technology-specific logic gates found in the library on the timing critical paths. To reduce the hold violations buffers are inserted to add delay on data paths. If the net is too long then the net is broken and buffers are inserted to improve the transition which will ultimately improve the timing on data path and reduce the setup violation. Buffering - Buffers are inserted in the design to drive a load that is too large for a logic cell to efficiently drive. Q3: List the possible techniques to fix a timing violation.

Q2: What kinds of timing violations are in a typical timing analysis report? Explain! Timing Analysis (partition the timing graph)Д¬ONSTRAINTS: Mentioning that care must be taken to make sure that partition boundaries are consistent when integrating the results back together. Others may be accepted if youВ gave a reasonable explanation of why you can or cannot use parallel computingВ in a particular stage of the flow. WHAT STAGES: The following answers are acceptable.

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